Fast timing analysis of clock networks considering environmental uncertainty

Dynamic power management can significantly introduce environmental uncertainties such as non-uniform temperature gradients and supply voltage fluctuations. This can bring many challenges for the system-level timing verification such as for global clock networks. This paper presents a fast verification of clockskew by an incremental-SVD-based compact modeling assisted with adaptive sampling. Firstly, an incremental-SVD is developed to perform an efficient update of environmental uncertainties avoiding a repeated full SVD. Secondly, an adaptive sampling is presented to build accurate models to sample clock and clock-skew for generating macromodels in a wide frequency range. Experiments on a number of clock networks show that when compared to the traditional fast TBR method, our macromodeling by incremental-SVD and adaptive sampling can significantly reduce the runtime with a similar accuracy. In addition, when compared to the Krylovsubspace-based method, our macromodeling further reduces the waveform error with a similar runtime. The work of Hai Wang and Sheldon X.-D. Tan is funded in part by NSF grant under no. CCF0448534, CCF-1017090 and CCF-1116882 and in part by National Natural Science Foundation of China (NSFC) grant under no. 60828008. The work of Hao Yu was supported by Singapore MOE Tier2 fund: MOE2010-T2-2-037.